1. Field of the Invention
The present invention relates to a semiconductor integrated circuit; and, more particularly, to a delay locked loop for use in synchronous dynamic random access memory, which is capable of obtaining a fast locking time and a reduced jitter.
2. Description of the Prior Art
For achieving a high speed operation in a semiconductor memory device, a synchronous dynamic access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Generally, when data are outputted in synchronization with the external clock signal, a skew between the external clock, signal and the output data is occurred. In the SDRAM, a delay locked loop (DLL) can be used to compensate for the skew between an external clock signal and an output data, or an external clock signal and an internal clock signal.
A digital DLL is implemented with a plurality of unit delay elements that are coupled in series. For increasing a resolution, a unit delay time should be minimized. As the unit delay time becomes smaller, however, more unit delay elements are needed. Consequently, power consumption as well as a chip size is increased much more.